Degree Programme in Wireless Communications Engineering Sdr Implementation of Ieee 802.15.4 Phy on Transport Triggered Architecture Processor

Ever evolving wireless communication standards, reduced time-to-market and a need for flexibility and interoperability of multiple wireless communication technologies on a single device are the driving factors behind implementation of wireless standards on Software Defined Radios (SDR) platforms. The concept behind SDR is to implement as much functionality on software as possible. SDR provide greater interoperability and programmability compared with traditional hardwired implementation at the cost of higher power consumption and market cost. SDR is the driving technology for the next generation of co-operative and cognitive radios. For implementing an SDR, the existing wireless communication algorithms needs to be modified and an appropriate hardware platform needs to be selected. The IEEE 802.15.4 LR-WPAN standard requires low cost and low-power consuming devices. The data rate requirements are also low (such as 250 kbps). Traditionally, the devices compliant with the standard are hardwired system-on-chip implementation which provides benefit in terms of power and cost. Recently, there has been significant effort on modeling the IEEE 802.15.4 SDR systems which provide greater interoperability and programmability of the devices. In this study, Transport Triggered Architecture (TTA) based Application Specific Processor is selected for SDR implementation of the IEEE 802.15.4 2.4 GHz physical layer for studying the performance of such system in terms of Bit-Error-Rate, CPU cycle count, and processor chip area. As part of this work, different SDR frameworks like GNU Radio, Matlab-Simulink etc. were evaluated for their feasibility of providing an agile platform for the development. These existing frameworks need an operating system for their execution and are not suitable for stand-alone systems such as a TTA based processor. The work also includes the study of different receiver algorithms and design choices for the transceiver implementation. Based on existing literature and Matlab modeling, Asynchronous Zero-Crossing Detector (AZCD) based non-coherent receiver algorithm is selected for the implementation. The algorithm provides the required BER performance with very less complex computation and is suited for low power and low chip area implementations. The transmitter and receiver are implemented on single-core TTA processors which provide the required performance in terms of BER and data throughput. The processors designed need a very low silicon area and clock frequency for their realization.